1. Field of the Invention
The present invention relates to the field of fabrication of integrated circuits, and, more particularly, to a method and structures for estimating an overlay accuracy and a pattern placement error (PPE) in forming and patterning stacked material layers used for fabricating microstructural features.
2. Description of the Related Art
The fabrication of microstructures, such as integrated circuits, requires tiny regions of precisely controlled size to be formed in a material layer of an appropriate substrate, such as a silicon substrate, a silicon-on-insulator (SOI) substrate, or other suitable carrier materials. These tiny regions of precisely controlled size are generated by patterning the material layer by performing photolithography, etch, implantation, deposition, oxidation processes and the like, wherein, typically, at least in a certain stage of the patterning process, a mask layer may be formed over the material layer to be treated to define these tiny regions. Generally, a mask layer may consist of or may be formed by means of a layer of photoresist that is patterned by a lithographic process. During the lithographic process, the resist may be spin-coated onto the wafer surface and then selectively exposed to ultraviolet radiation through a corresponding lithography mask, such as a reticle, thereby imaging the reticle pattern into resist layer to form a latent image therein. After developing the photoresist, depending on the type of resist, positive resist or negative resist, the exposed portions or the non-exposed portions are removed to form the required pattern in the layer of photoresist.
Since the dimensions of the patterns in sophisticated integrated circuits are steadily decreasing, the equipment used for patterning device features have to meet very stringent requirements with regard to resolution and overlay accuracy of the involved fabrication processes. In this respect, resolution is considered as a measure for specifying the consistent ability to print minimum size images under conditions of predefined manufacturing variations. One important factor in improving the resolution is represented by the lithographic process, in which patterns contained in the photomask or reticle are optically transferred to the substrate via an optical imaging system. Therefore, great efforts are made to steadily improve optical properties of the lithographic system, such as numerical aperture, depth of focus and wavelength of the light source used.
The quality of the lithographic imagery is extremely important in creating very small feature sizes. Of at least comparable importance, however, is the accuracy with which an image can be positioned on the surface of the substrate. Typically, microstructures, such as integrated circuits, are fabricated by sequentially patterning material layers, wherein features on successive material layers bear a spatial relationship to one another. Each pattern formed in a subsequent material layer has to be aligned to a corresponding pattern formed in the previously patterned material layer within specified registration tolerances. These registration tolerances are caused by, for example, a variation of a photoresist image on the substrate due to non-uniformities in such parameters as resist thickness, baking temperature, exposure dose and time and development conditions. Furthermore, non-uniformities of the etch processes can also lead to variations of the etched features. In addition, there exists an uncertainty in overlaying the image of the pattern of the current material layer to the etched or otherwise defined pattern of the previously formed material layer while photolithographically transferring the image of the photomask onto the substrate. Several factors contribute to the ability of the imaging system to perfectly overlay two layers, such as imperfections within a set of masks, temperature differences at the different times of exposure, and a limited registration capability of the alignment tool. As a result, the dominant criteria for determining the minimum feature size that may finally be obtained are the resolution for creating features in individual substrate layers and the total overlay error to which the above explained factors, in particular the lithographic process, contribute.
Therefore, it is essential to steadily monitor the resolution, i.e., the capability of reliably and reproducibly creating the minimum feature size, also referred to as critical dimension (CD), within a specific material layer and to steadily determine the overlay accuracy of patterns of material layers that have been successively formed and that have to be aligned to each other.
In overlay metrology, typically two independent structures, that is one structure in each layer to be printed, are formed by the specified manufacturing processes and the displacement between the centers of symmetry is determined. Frequently, so-called box-in-box marks are used, which are concentrically patterned in each of the layers by measuring their displacement in units of pixels of a charge coupled device (CCD) onto which the concentric alignment marks are imaged during the measurement process. For ever-decreasing feature sizes of microstructures, however, the detection of a displacement, and thus the quantification of an overlay error between both overlay marks, on the basis of edge finding routines may no longer be adequate. Therefore, recently, so-called advanced imaging metrology (AIM) marks are increasingly used to enhance overlay metrology reliability. AIM marks exhibit a periodic structure, thereby enabling utilization of highly powerful metrology techniques. Hence, increased performance of the overlay metrology may be obtained by using periodic overlay marks. With decreasing feature sizes, however, a discrepancy between overlay characteristics within a single die and the significantly larger structures of the overlay marks, which are typically located in the scribe line of the substrate, may be observed, thereby rendering measurement data obtained from the target in the scribe line less reliable. One reason for this discrepancy resides in the fact that the lithography tool may image fine structures, as are typically found within the die, such as gate electrodes, shallow trench isolation (STI) structures and the like, in a different manner compared to relatively large structures, which are typically used to form overlay marks. This pattern and size dependent phenomenon of a different degree of overlay is called pattern placement error (PPE). Consequently, the pattern placement error has to be quantified in order to correct the results of the overlay measurements obtained from the overlay marks within the scribe line with respect to the contribution to actual microstructural features within the die. The pattern placement error can conveniently be measured by so-called simultaneous AIM overlay marks, as will be described in more detail with reference to FIGS. 1a and 1b. 
FIG. 1a schematically shows a top view of an overlay measurement structure 100, which may be formed on a specified substrate portion 101, which is typically located within a scribe line of any appropriate substrate bearing a plurality of dies, within which actual functional microstructural features are formed. The overlay measurement structure 100 may be provided in the form of an AIM mark, that is, the structure 100 may comprise a periodic structure, which may enable the measurement of an overlay error in at least two independent directions. In this example, the structure 100 comprises four outer periodic structures 101o, two of which have lines and spaces oriented along an x-direction, while the remaining two periodic structures 101o have lines and spaces oriented substantially along the y-direction. Similarly, four inner periodic structures 101i are provided, wherein two of the inner periodic structures 101i have lines and spaces oriented in the x-direction and are placed adjacent to the respectively oriented outer structures 101o. Moreover, the remaining two inner structures 101i are oriented along the y-direction and are located adjacent to the corresponding outer structures 101o. Hereby, the outer structures 101o and the inner structures 101i are formed in different layers so that the combined overlay measurement structure 100 contains information on the overlay accuracy of the two layers including the periodic structures 101o and 101i, respectively, with respect to the x- and y-directions.
The structure 100 may be formed according to the following process flow, wherein it may be assumed that the outer periodic structure 101o may be formed first in a corresponding device layer, such as a layer receiving STI trenches. It should be appreciated that the selection of a respective sequence of material layers is arbitrary and the principles of the formation of the structure 100 may correspondingly be applied to any front-end or back-end process sequence involving a photolithography step for patterning a further material layer on top of one or more previous layers. A pattern according to the outer periodic structures 101o may be imaged by photolithography into a corresponding resist layer that is formed above the substrate under consideration and also above the substrate portion 101. Consequently, in any die regions (not shown), a corresponding pattern for, for instance, STI trenches may be defined simultaneously with the outer periodic structures 101o. After the development of the resist layer, a corresponding well-approved sequence of manufacturing steps including anisotropic etch techniques, deposition techniques, chemical mechanical polishing (CMP), and the like may be performed in order to form the corresponding patterns in the die and also the periodic structures 101o. Thereafter, a process sequence may be performed for forming microstructural features on the previously patterned layer, such as gate electrode structures, polysilicon lines and the like. Hence, a plurality of well-established oxidation and deposition processes may be carried out, such as the formation of a thin gate insulation layer and a subsequent deposition of a gate electrode material and the like, followed by a further photolithography process for patterning the structure, thereby simultaneously forming the periodic inner structures 101i in the substrate portion 101. As previously pointed out, the individual lines and spaces of the inner and outer periodic structures 101i, 101o may not be formed in accordance with the same design rules, but may be patterned in accordance with metrology requirements so as to enhance the detection of any offset between the inner and outer periodic structures 101i, 101o. Thus, the pitch of the inner and outer periodic structures 101i, 101o may be significantly larger compared to any critical dimensions of actual device features formed within the die regions. Consequently, an overlay accuracy with respect to the x- and y-directions may be estimated with moderately high precision for the overlay measurement structure 100 itself, but may not allow a precise estimation of the overlay accuracy within actual die regions having formed therein structural features of significantly less critical dimensions compared to dimensions in the overlay measurement structure 100. Therefore, in addition to the overlay structure 100, the so-called simultaneous AIM overlay marks are frequently used, in which at least some of the features of the periodic structures contain a “fine structure” formed in accordance with the respective design rules for actual device features in the die regions.
In determining the overlay accuracy of the two different layers represented by the inner and outer periodic structures 101i, 101o, a metrology tool, such as a tool for obtaining optical data, is aligned with respect to the structure 100 and data are obtained from respective working zones 110i, 110o, which define a respective measurement area in each of the periodic structures 101i, 101o. For example, the position of the lines and spaces within the respective working zone 110i corresponding to an inner periodic structure 101i may be determined and may then be compared with the corresponding position information of lines and spaces determined for the corresponding outer periodic structure 101o. On the basis of this information, the required information with respect to overlay accuracy in the x- and y-direction may be obtained.
FIG. 1b schematically shows a simultaneous AIM overlay measurement structure 150, which may be formed in the substrate portion 101, in addition to the overlay measurement structure 100. The simultaneous overlay measurement structure 150 may comprise inner periodic structures 151i and outer periodic structures 151o, wherein one of the inner and outer periodic structures 151i, 151o also include a fine structure, which in the example shown is represented by 152 formed in the outer periodic structures 151o. It should be appreciated that the inner periodic structures 151i as well as the outer periodic structures 151o are formed within the same material layer, for instance in the STI layer, as previously explained. Regarding the formation of the simultaneous overlay measurement structure 150, the same criteria apply as previously explained with reference to the structure 100, except for using a different lithography mask to provide the fine structure 152 in one of the inner and outer periodic structures 151i, 151o. Moreover, an amount of offset between the inner and outer periodic structures 151i, 151o is to be set to a predefined value, preferably zero, by design, thereby enabling the determination of any shift of the fine structure 152, which may also be referred to as a segmented structure, with respect to the periodic structures 151i without fine structure, that is, the non-segmented periodic structure 151i. 
As previously explained, due to the pattern placement error, a corresponding shift may be detected in the form of an apparent overlay error, and this measure may be used for assessing the contribution of the pattern placement error within a die region to obtain a measure for correcting the actual overlay error between two different device layers measured by the overlay measurement structure 100, as shown in FIG. 1a. Thus, during the measurement of sophisticated microstructural devices, at least two overlay measurement structures, such as the structure 100 and 150, have to be provided, wherein, in highly sophisticated applications, even one simultaneous overlay measurement structure 150 is provided for each of the layers of which the overlay accuracy must be determined. Thus, three overlay measurement structures, that is, one for overlay, i.e., the structure 100, and two for the PPE characterization of two different lithography layers, i.e., the structure 150, may be provided. FIG. 1c schematically illustrates this situation. Here, the three overlay structures 100, 150 and 150 are provided, wherein each of the two structures 150 is formed in a different layer.
Due to the ever-increasing demand on enhanced productivity and reduced manufacturing costs, the dimensions of scribe lines may also be reduced, thereby significantly restricting the available space for any measurement areas within the scribe lines.
In view of this situation, there exists a need for an enhanced technique for determining overlay errors, while avoiding or at least reducing the effects of one or more of the problems identified above.